发明名称 IMAGE SIGNAL REDUCING METHOD AND MULTIPLICATOR
摘要 PROBLEM TO BE SOLVED: To provide an image signal reducing method and a multiplcator that reduce an image signal even with simple and compact constitution. SOLUTION: A multiplying circuit 7 multiplies a signal source output signal Vs output from a signal source 3 by a frequency-division output signal Vdiv generated by halving the frequency of the signal source output signal Vs by a frequency dividing circuit 5 to generate a conversion signal Vcon including a main signal and an image signal. The frequency-division signal Vdiv is amplified by 1/2 time through an amplifying circuit 9 to generate an image-reduced signal Vred. Then the conversion signal Vcon output from the multiplying circuit 7 and the image-reduced signal Vred output from the amplifying circuit 9 are input to a subtracting circuit 11, which subtracts the image-reduced signal Vred from the conversion signal Vcon and outputs an output signal Vout wherein the image signal is reduced. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2006339942(A) 申请公布日期 2006.12.14
申请号 JP20050160987 申请日期 2005.06.01
申请人 TOYOTA INDUSTRIES CORP 发明人 MATSUOKA HIDEKI
分类号 H03D7/18 主分类号 H03D7/18
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