| 摘要 |
PROBLEM TO BE SOLVED: To suppress clock skew even when supply voltages supplied to two circuit blocks are different. SOLUTION: A first clock buffer 25 is arranged in a clock signal supplying passage to a second circuit block 30 to which one supply voltage VDD2 is supplied from an interconnect line PWS, and a second clock buffer 35 is arranged in a clock signal supplying passage to the first circuit block 20 to which the other supplying voltage VDD1 is supplied from an interconnect line PWM. The first clock buffer 25 is equal to a clock tree 22 of counterpart clock signal supplying passage in the number of stage, and receives the same supply voltage VDD1 simultaneously. The second clock buffer 35 is equal to a clock tree 32 of counterpart clock signal supplying passage in the number of stage, and receives the same supply voltage VDD2 simultaneously. COPYRIGHT: (C)2007,JPO&INPIT
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