发明名称 Low power NROM memory devices
摘要 A buried bipolar junction is provided in a charge trapping transistor memory device. During a write operation electrons are injected into a surface depletion region of the memory cell transistors. These electrons are accelerated in a vertical electric field and injected over a barrier to a charge trapping dielectric layer of the memory cells.
申请公布号 US2006279998(A1) 申请公布日期 2006.12.14
申请号 US20050151952 申请日期 2005.06.14
申请人 MICRON TECHNOLOGY, INC. 发明人 FORBES LEONARD
分类号 G11C16/04 主分类号 G11C16/04
代理机构 代理人
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