| 摘要 |
<P>PROBLEM TO BE SOLVED: To obtain a PLL circuit which suppresses phase variations of an output clock using a small-scaled control circuit. <P>SOLUTION: A PLL circuit for suppressing phase variations of an output clock comprises: a phase comparing means 2 for detecting a phase difference between an input signal and an output clock of a VCO; an LPF 3 for inputting the output of the phase comparing means and passing only a low frequency component; an ordinary phase error detecting means 5 for inputting the output of the LPF and detecting an ordinary phase error of the PLL circuit; a VCO oscillation frequency offset control means 6 for inputting the output of the ordinary phase error detecting means and generating a VCO oscillation frequency offset control voltage; and a VCO 4 including a VCO oscillation frequency control terminal for inputting the output of the LPF and a VCO oscillation frequency offset control terminal which inputs the output of the VCO oscillation frequency offset control means. <P>COPYRIGHT: (C)2007,JPO&INPIT |
