| 摘要 |
Disclosed are a delay circuit and a semiconductor device including the same. The delay circuit comprises a plurality of delay blocks, which are connected in series, and a driving portion adapted to logically combine signals transmitted by the plurality of delay blocks to generate a delay circuit output signal. Each of the plurality of delay blocks delays an output signal from an immediately previous delay block and transmits a resulting delayed output signal to a next delay block when delay operation is enabled based on a control signal. However, where the delay operation of a delay block is disabled based on the control signal, the delay block transmits the output signal of the immediately previous delay block to the driving portion.
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