An output buffer circuit is provided to secure a time for transmitting data and perform a high-speed data transmission process by not requiring a time for compensating an offset voltage. An input terminal(301a-301f) receives an input voltage and outputs an output voltage. A class AB output terminal(304a,304b) increase the current applied to the output terminal when a difference between the input terminal and the output terminal is more than 0. A floating current source(302a-302d) biases the class AB output terminal. A summing circuit(303a-303h) is connected with the input terminal, the floating current source, and the class AB output terminal in order to sum up the current of the input terminal and the internal current of the floating current source. An offset sensing circuit(305a-305f) is connected with an input terminal and includes a plurality of transistors to sense an offset voltage. An offset compensation circuit(306a-306h) is connected with the input terminal and the offset sensing circuit and includes a plurality of transistors to compensate the offset voltage.
申请公布号
KR20060124895(A)
申请公布日期
2006.12.06
申请号
KR20050046568
申请日期
2005.06.01
申请人
SAMSUNG ELECTRO-MECHANICS CO., LTD.
发明人
LEE, YOUN JOONG;CHOI, WON TAE;PARK, CHAN WOO;KIM, BYOUNG HOON