发明名称 |
Control and supervisory signal transmission system |
摘要 |
A parent station output section changes a duty factor between a period in which a control data signal is at a level (high-potential low-level) lower than a power supply voltage Vx but higher than high-level signal in other circuit portions and a subsequent period in which the control data signal is at the power supply voltage Vx level to convert the control data signal into a serial pulse voltage signal and output the voltage signal onto data signal lines D+ and D- in accordance with each data value in the control data signal inputted from a controller in each cycle of a clock. |
申请公布号 |
HK1054609(A1) |
申请公布日期 |
2006.12.01 |
申请号 |
HK20030106868 |
申请日期 |
2003.09.24 |
申请人 |
ANYWIRE CORPORATION |
发明人 |
YOSHITANE SAITOU;KENJI NISHIKIDO;KOUJI YUKAWA;YASUSHI MORI |
分类号 |
G05B15/02;G08C;G05B19/042;G06F;H03K19/0175;H04B3/50;H04L12/40;H04L25/02;H04Q;H04Q9/00 |
主分类号 |
G05B15/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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