| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a shift register operated favorably without providing a level shifter. <P>SOLUTION: The first clocked inverter (CK) of a (2n-1)-th stage is operated according to the output of the 2nd CK of the same stage as that of the first output of a previous sage and a 1st CK signal, the 2nd CK of the (2n-1)-th stage is operated according to the 2nd output of the previous sage, the output of the 1st CK of the (2n-1)-th stage and the first CK signal. One of the 1st and 2nd outputs is equal to the potential of a VDD, while the other is equal to the potential of VSS. The 1st CK of a 2n-th stage is operated according to the 3rd output of a previous stage, the output of the 2nd CK of the 2n-th stage, and a 2nd CK signal, the 2nd CK of the 2n-th stage is operated according to the 4th output of a previous stage, the output of the 1st CK of the 2n-th stage, and the 2nd CK signal, and one of the 3rd and 4th outputs is equal to the potential of the VDD while the other is equal to the potential of the VSS, and the 2nd CK signal is an inversion signal of the 1st CK signal and the amplitude of the CK signal is smaller than the power supply potential. <P>COPYRIGHT: (C)2007,JPO&INPIT |
