发明名称 |
Low-cost, low-voltage single-layer polycrystalline EEPROM memory cell integration into BiCMOS technology |
摘要 |
An EEPROM memory transistor having a floating gate. The floating gate is formed using a BiCMOS process and has a first sinker dopant region proximate to a tunnel diode window, and a second sinker dopant region proximate to a coupling capacitor region. An optional third sinker region may be formed proximate to a source junction of the EEPROM memory transistor. Also, a shallow trench isolation (STI) region may be formed between the first and second sinker dopant regions.
|
申请公布号 |
US2006267071(A1) |
申请公布日期 |
2006.11.30 |
申请号 |
US20050136140 |
申请日期 |
2005.05.24 |
申请人 |
CARVER DAMIAN A;CHAUDHRY MUHAMMAD I |
发明人 |
CARVER DAMIAN A.;CHAUDHRY MUHAMMAD I. |
分类号 |
H01L29/788 |
主分类号 |
H01L29/788 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|