| 摘要 |
A ferroelectric memory, upon reading of a memory cell array, in which the plate line PL is charged to the power supply potential VDD by a driving control circuit prior to driving of the relevant word line WL. The bit lines BL and /BL are charged to the potential VDD by a timing control circuit, then the word line WL is driven. At this time, the lines BL and /BL are discharged by applying an equalizing signal EQ with predetermined pulse width to a reset circuit.
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