发明名称 Method and apparatus for parallel execution pipeline data storage in a computer memory
摘要 A computer system having a plurality of parallel execution pipelines which may generate data for storing in a memory, data from the pipelines may be stored in a queue prior to accessing the memory and the system includes circuitry for reordering data from the different pipelines before inserting onto the queue.
申请公布号 US7143247(B1) 申请公布日期 2006.11.28
申请号 US20000563315 申请日期 2000.05.02
申请人 STMICROELECTRONICS S.A. 发明人 GROSSIER NICOLAS
分类号 G06F12/00;G06F9/38 主分类号 G06F12/00
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