A parallel multiplier for a finite field is provided to usefully apply to implementation of hardware in encryption-related application fields by having the same space/time complexity as the most efficient Reyhani-Masoleh and Hansan multiplier. An AB multiplier(100) multiplies input 'A' and 'B' by a formula-1. An 'x' function part(110) operates the input 'A' and 'B' by a formula-2. An S1 function part(120) performs right cyclic shift according to a formula-3 by using a result value of the 'x' function part. A BTX1 multiplier(130) maps/adds the result value of the AB multiplier and the S1 function part to each cipher of the final output by a formular-4.
申请公布号
KR100653358(B1)
申请公布日期
2006.11.27
申请号
KR20050090141
申请日期
2005.09.27
申请人
KOREA UNIVERSITY INDUSTRY AND ACADEMY COOPERATIONFOUNDATION
发明人
LIM, JONG IN;KIM, CHANG HAN;JANG, NAM SOO;KIM, SO SUN