| 摘要 |
A CMOS(complementary metal oxide semiconductor) inverter cell is provided to reduce parasitic resistance and parasitic capacitance in a circuit and improve the response speed of an inverter by including a relatively small area in comparison with a conventional inverter cell. A straight gate pattern(301) comes in contact with at least one surface of a cell border line. A first active region pattern(302) has a channel region overlapped with the gate pattern and a source/drain region at both sides of the channel region. A second active region pattern(303) has a channel region overlapping the gate pattern and a source/drain region at both sides of the channel region. A first metal line pattern(304) comes in contact with at least one surface of the cell border line, positioned on the first active region. A second metal line pattern(305) comes in contact with one surface of the cell border line, positioned on the first active region. A third metal line pattern(306) is positioned on an extension line of the second metal line pattern, coming in contact with the other surface of the cell border line. A plurality of contacts(CNT) are formed on the source/drain region. The first metal line pattern commonly connects the drain regions of the first and second active region patterns. The second metal line pattern connects the source region of the first active region pattern with a first power source. The third metal line pattern connects the source region of the second active region pattern with a second power source.
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