| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To overcome the problem that pipeline stall occurs when misalignment load instructions are issued or a cache miss is present in cache access, even if a microprocessor comprises a non-blocking load function. <P>SOLUTION: A load store unit 22 includes: a Top register 103 for storing a pre-load value of a load destination register; a misalignment instruction decision unit 104 for deciding whether the load instructions issued from an instruction decoding unit 13 are the misalignment load instructions; and a save register 106 that can store data held by the Top register 103. When the misalignment instruction decision unit 104 decides that the load instructions are the misalignment load instructions, the data stored in the Top register 103 is stored in the save register 106, and the Top register 103 is made available for the following instructions issued by the instruction decoding unit 13. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
