Mixer circuit, receiver comprising a mixer circuit method for generating an output signal by mixing an input signal with an oscillator signal

摘要

The invention relates to a mixer circuit, a receiver comprising a mixer circuit, and a method of mixing an input signal with an oscillator signal. A mixer circuit 300 according to the invention comprises a first input node 301 and a second input node 302 for receiving an input signal Vin, a first output node 321 and a second output node 322, voltage to-current conversion means R 1 a, R 1 b, R 2 a, R 2 b, and switching means M 1, M 2, M 3, M 4 operatively coupled to each other and to the first input node 301, the second input 305 node 302, the first output node 321, and the second output node 322 to generate a mixed input signal the first output node 321 and the second output node 322 in response to an oscillator signal. The voltage-to-current conversion means R 1 a, R 1 b, R 2 a, R 2 b comprises a first voltage-to current converter RI a, R 2 a for generating a first current at a first Vdac switching node 311 and a third current at a third switching node 313 in response to the input signal Vin, and a second voltage-to-current converter R 1 b, R 2 b for generating a second current at a second switching node 312 and a fourth current a fourth switching node 314 in response to the input signal Vin. The switching means M 1, M 2, M 3, M 4 is arranged to couple the second switching node 312 to the second output node 322 and the third switching node 313 to the first output node 321 during a first phase phi 1 of the oscillator signal; and the first switching node 311 to the first output node 321 and the fourth switching node 314 to the second output node 322 during a second phase phi 2 of the oscillator signal. As a result first and third switching nodes 311, 313 are isolated from respectively second and fourth switching node 312, 314. This prevents cross-over distortion from parasitic capacitances associated with first and third switching nodes 311, 313 via respective switches M 2 and M 4, and vice versa from parasitic capacitances associated with second and fourth switching nodes 312, 314 via respective switches M 1 and M 3.