| 摘要 |
A multilayer interconnect configuration is formed on a semiconductor substrate where a semiconductor integrated circuit is provided. Each layer of the multilayer interconnect configuration has a plurality of pads. Except for the pads of the top layer, the area of the pads is reduced relative to the pads of the top layer. The pad area is reduced by forming a plurality of openings in the pads, or by forming a plurality of notches in the pads whereby the pads have a comb configuration. The capacitance can be significantly reduced by decreasing the area. The reduction of capacitance allows for significantly reducing the effect of a low-pass filter produced from the interconnect metal resistance and the pad capacitance, which slows down the circuit operation. Therefore the high-speed operation can avoid degradation.
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