| 摘要 |
A buffer control circuit for reducing power consumption, and a semiconductor memory device for a memory module including the same and a control operation method thereof are provided to reduce unnecessary power consumption due to a data input buffer, by generating a buffer control signal on the basis of a control signal for a termination device. A first control signal generator(110) generates an internal buffer control signal, in response to write latency signals and internal control signals. A second control signal generator(120) generates a buffer control signal, in response to the internal buffer control signal and a termination control signal. The termination control signal is enabled for a predetermined time, during a read operation of a semiconductor memory device including the termination device and the buffer control circuit, wherein the predetermined time is determined by a read command, CAS latency and burst length.
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