Embodiments of the present invention relate to a system and method for comparatively increasing processor throughput and relieving pressure on the processor's scheduler and register file by diverting instructions dependent on long-latency operations from a flow of the processor pipeline and re-introducing them into the flow when the long-latency operations are completed. In this way, the instructions do not tie up resources and overall instruction throughput in the pipeline is comparatively increased.
申请公布号
WO2006039201(A3)
申请公布日期
2006.11.16
申请号
WO2005US34145
申请日期
2005.09.21
申请人
INTEL CORPORATION (A CORPORATION OF DELAWARE);AKKARY, HAITHAM;RAJWAR, RAVI;SRINIVASAN, SRIKANTH