发明名称 Handling defective memory blocks of NAND memory devices
摘要 Apparatus and methods are provided. A NAND memory device has a memory array comprising a plurality of memory blocks and a volatile latch coupled to each of the memory blocks for selectively preventing testing of the respective memory block coupled thereto when that memory block is a known defective block. A non-volatile latch may also be coupled to each of the memory blocks for permanently preventing access, during normal operation of the memory device, to the respective memory block coupled thereto when that memory block is a known defective block.
申请公布号 US2006256633(A1) 申请公布日期 2006.11.16
申请号 US20060487857 申请日期 2006.07.17
申请人 MICRON TECHNOLOGY, INC. 发明人 LOUIE BENJAMIN;YIP AARON
分类号 G11C29/00;G11C8/02;G11C16/04;G11C29/26 主分类号 G11C29/00
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