| 摘要 |
PROBLEM TO BE SOLVED: To provide a NAND gate circuit and a dynamic circuit using bulk semiconductor for achievement of highly miniaturized transistors with enhanced performance. SOLUTION: Source/drain diffusion layers each comprise a low resistivity region and a shallow extension region with a lower impurity concentration than that of the low resistivity region. A channel region between the source/drain diffusion layers is formed with a first conduction type first impurity-doped layer, a second conduction type second impurity-doped layer formed under the first impurity-doped layer, and a first conduction third impurity-doped layer formed under the second impurity-doped layer. The first impurity-doped layer is equal to or less in junction depth than the extension regions of the source/drain diffusion layers, and the second impurity doped layer has impurity concentration and thickness to be fully depleted due to a built-in potential as created between the first and third impurity-doped layers. COPYRIGHT: (C)2007,JPO&INPIT
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