发明名称 Apparatus and method for controlling address conversion buffer
摘要 A method for controlling an address conversion buffer, constituted on a processor capable of executing a plurality of threads simultaneously on one core, includes registering address conversion information in an entry of the address conversion buffer that includes a first memory area (CAM) usable by one of the threads and a second memory area (RAM) shared among all the threads, allocating a part of the second memory area as a swap area of the first memory area, and transferring data in the swap area to the first memory area, based on thread switching executed by the processor.
申请公布号 EP1622034(A3) 申请公布日期 2006.11.02
申请号 EP20040257419 申请日期 2004.11.30
申请人 FUJITSU LIMITED 发明人 DOI, MASANORI;YAMAZAKI, IWAO
分类号 G06F12/10 主分类号 G06F12/10
代理机构 代理人
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