发明名称 |
Substrate configurable JTAG ID scheme |
摘要 |
A circuit generally comprising a core circuit and a test access port circuit. The core circuit may be configurable among a plurality of functions in response to a signal. The test access port circuit may be configured to determine an identification value in response to the signal.
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申请公布号 |
US7131033(B1) |
申请公布日期 |
2006.10.31 |
申请号 |
US20020176976 |
申请日期 |
2002.06.21 |
申请人 |
CYPRESS SEMICONDUCTOR CORP. |
发明人 |
ROPER WESTON;GRIVNA EDWARD L. |
分类号 |
G06F11/00 |
主分类号 |
G06F11/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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