发明名称 Delay distribution calculation method, circuit evaluation method and false path extraction method
摘要 Delay distribution in an integrated circuit is calculated while taking into account a correlation of performance between interconnects or elements in the integrated circuit, thereby improving estimation accuracy. Circuit information, performance distribution information of the interconnects or elements in the integrated circuit, and correlation information of performance between the interconnects or elements are input. A vertex is selected for calculation, and a correlation between delay distribution at the selected vertex and delay distribution in a partial circuit including the selected vertex is calculated based on the performance distribution information and the correlation information.
申请公布号 US7131082(B2) 申请公布日期 2006.10.31
申请号 US20030739309 申请日期 2003.12.19
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 TSUKIYAMA SHUJI;TANAKA MASAKAZU;FUKUI MASAHIRO
分类号 G06F17/50;G05B19/042 主分类号 G06F17/50
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