| 摘要 |
A test method of a semiconductor device including a DRAM(Dynamic Random Access Memory) is provided to decrease test consumption time and to increase failure detection range by applying a sufficient stress voltage. A disturbance test is performed in a state of applying an HVS voltage to a gate of a cell transistor. When performing the disturbance test, test data are recorded to a memory cell matrix. An operation for reading a memory cell connected to a word line is performed sequentially to all the word lines. When performing the operation for reading the memory cell, activating a first word line, bit lines are read sequentially. The memory cell matrix is refreshed.
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