发明名称 |
ACS circuit and viterbi decoder with the circuit |
摘要 |
An ACS circuit and a Viterbi decoder with the circuit. The Add-Compare-Select (ACS) circuit comprises: two registers for storing two previous candidate state metrics; a first adder for adding the value stored in the first register and a first branch metric to generate a first addition result; a second adder for adding the value stored in the second register and the first branch metric to generate a second addition result; a comparator for comparing the values stored in the first register and the second register to generate a decision bit; and a multiplexer for selecting either the first addition result or the second addition result as a new output candidate state metric according to the decision bit. Due to the parallel processing of the adders and the comparator, the processing speed of a Viterbi decoder with the ACS will be increased.
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申请公布号 |
US7127667(B2) |
申请公布日期 |
2006.10.24 |
申请号 |
US20030412339 |
申请日期 |
2003.04.14 |
申请人 |
MEDIATEK INC. |
发明人 |
CHEN HONG-CHING;SHEN WANG, LEGAL REPRESENTATIVE DER-TSUEY |
分类号 |
G11B20/14;G11B20/18;H03M13/41 |
主分类号 |
G11B20/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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