| 摘要 |
An electrostatic protection device for a semiconductor circuit is provided to protect an internal circuit by reducing a primary triggering voltage and by improving a secondary break down current. An N well(140) is formed on a P-type substrate(100). A P well(142) is formed inside the N well. A gate(102) is formed in a surface of the P well. An N+ source(104) and an N+ drain(106) are formed at the N well and the P well of both sides of the gate, respectively. A P+ pickup(108) is formed in a surface of the P-type substrate of a left side of the source. The drain(106) is connected to an input/output pad. The source and the pickup are connected to the ground pad. The P well is formed in the P-type substrate to enclose a lower region of the gate and the drain including the lower region of the gate and the drain.
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