| 摘要 |
A semiconductor flash memory device with increased gate coupling ratio and a method of preparing this flash memory device. The semiconductor flash memory device includes a notched floating polysilicon gate. The notches are at the interface between the floating polysilicon layer and the tunneling dielectric layer. The notches reduce the capacitance between the floating polysilicon and the channel region. The reduced capacitance results in the increased gate coupling ratio. The degree of capacitance reduction, which affects the gate coupling ratio increase, is controlled by the width of the notches. The floating polysilicon gate etch includes a first anisotropic etch and a second isotropic etch. The widths of the notches are controlled by the etch time of the isotropic etch.
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