发明名称 DESIGNING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a designing method of a semiconductor integrated circuit with which a voltage drop value of respective nodes can be suppressed even if leakage current due to gate leakage and channel leakage occurs. SOLUTION: Leakage current obtained by adding gate leakage and channel leakage is calculated at every node in the semiconductor integrated circuit. Since a buffer is inserted into the node where the voltage drop valueΔVg by calculated leakage current exceeds a threshold, a fault that voltage of the node becomes instable owing to gate leakage and channel leakage does not occur and reliability of the circuit improves. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2006286840(A) 申请公布日期 2006.10.19
申请号 JP20050103296 申请日期 2005.03.31
申请人 TOSHIBA CORP 发明人 IDAKA YASUHITO
分类号 H01L21/82;G06F17/50;H01L21/822;H01L27/04 主分类号 H01L21/82
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