发明名称 ENCODER, DECODER, AND ENCODING METHOD
摘要 PROBLEM TO BE SOLVED: To provide an encoder, decoder, and encoding method capable of encoding and decoding data with a small circuit. SOLUTION: A second input register 1112 and first input register 1111 are linked to each other and store consecutive input data. When zero run which violates G constraint is detected from the data stored in these two registers, data before and after G constraint violation are transferred by a zero run removal bus 1130 and synthesized in a temporary register 1150. Thus, by effectively using the mechanism of bus transfer, a circuit can be simplified, thereby realizing a small circuit. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2006286084(A) 申请公布日期 2006.10.19
申请号 JP20050104181 申请日期 2005.03.31
申请人 FUJITSU LTD 发明人 SAWADA MASARU;ITO TOSHIO;MORITA TOSHIHIKO
分类号 G11B20/14;H03M7/14 主分类号 G11B20/14
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