发明名称 MULTI-CPU SYSTEM
摘要 PROBLEM TO BE SOLVED: To provide a multi-CPU system capable of exclusive control to access to the same resource by a plurality of CPUs, by hardware without depending on an OS. SOLUTION: This multiCPU system is provided with posted write type bus bridge parts 103, 104 respectively corresponding one-to-one with two CPUs 101, 102. The bus bridge parts 103, 104 each have a semaphore control part 205. The semaphore control part 205 determines a value of an output side band signal (sem_out) of a side band signal line 115 (114) on the basis of a value (reg) set to a semaphore acquisition register 202, an input side band signal (sem_in) of the side band signal line 114 (115), and a state (a stack) of a priority order determination signal of a signal line 112 (113). COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2006285872(A) 申请公布日期 2006.10.19
申请号 JP20050107921 申请日期 2005.04.04
申请人 CANON INC 发明人 SUZUKI KATSUYA
分类号 G06F13/362;G06F9/52;G06F13/376 主分类号 G06F13/362
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