| 摘要 |
PROBLEM TO BE SOLVED: To suppress degradation in wiring performance due to a base layer covering a step. SOLUTION: A collector layer 2 containing an active region 2a surrounded by an element separation film 3 is formed on an Si substrate 1. A protective film 4 having an opening in a predetermined region on a side containing the active region 2a is provided on the separation region 3. An SiGe alloy layer 6 is formed on the active region 2a, and an Si film 7 and an n-type diffusion layer 13 are formed thereon. A polycrystalline Si film 8a and a silicide film 14a are formed on the layer 13. A p<SP>+</SP>diffusion layer 10a as an outer base layer is formed outside a region serving as an inner base layer of the alloy layer 6. The p<SP>+</SP>diffusion layer 10a is provided to cover the protective film 4 on the element separation region 3, and a spacer-like sidewall film n<SP>+</SP>diffusion layer 10b is provided on a step 4a' thus caused. Silicide films 14b, 14c and 14d for a low resistance layer of the outer base layer are formed on the surface of the p<SP>+</SP>diffusion layer 10a and the n<SP>+</SP>diffusion layer 10b. COPYRIGHT: (C)2007,JPO&INPIT
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