| 摘要 |
An input circuit including a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive a first signal and a second signal and to sample the first signal via the second signal and provide signal samples of the first signal. The second circuit is configured to receive a third signal and the signal samples and to update a second circuit output signal via the third signal and provide the updated second circuit output signal. The third circuit is configured to receive a clock signal and the second signal and to provide the third signal. The third circuit is also configured to synchronize edges in the third signal to edges in the second signal and edges in the clock signal.
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