SEMICONDUCTOR LOGIC CIRCUIT DEVICE TEST METHOD AND TEST PROGRAM

摘要

There are provided a semiconductor logic circuit device test method and a test program. It is possible to reduce the number of output changing scan flip-flops during capture operation, thereby reducing the capture power consumption, which in turn reduces the power voltage and reduce generation of an erroneous test. This can be achieved by embedding 0 or 1 in an unspecified bit X in a text cube so as to reduce the output changing scan flip-flops during capture operation, thereby converting the test tube into a test vector not containing the unspecified bit X. More specifically, a necessary conversion process is executed in accordance with the case when the unspecified bit X exists in a pseudo external input line (PPI) or a pseudo external output line (PPO) of the combination portion (11) or exists in both of them.