发明名称 Device and method for controlling data packet transfer
摘要 <p>An IEEE 1394 compliant bus controller (11) transfers data packets between connected nodes (1, 2, 3, 4, 23). The controller (11) includes a processor (13, 14) which divides a series of data into blocks and then stores the blocks in multiple packets (one block per packet) . The packets are then transferred over the bus from a source node to a destination node at equal intervals until the entire series of data has been transferred. An initialization prohibition unit (15, 17, 18, 19, 20, 22) prohibits initialization of the nodes during the data transfer which may be caused, for example, by hot plugging (connecting a new node to the bus) during the data transfer. <IMAGE></p>
申请公布号 EP1049023(B1) 申请公布日期 2006.10.11
申请号 EP20000302271 申请日期 2000.03.21
申请人 FUJITSU LIMITED 发明人 OI, KENJI;SHIMIZU, TAKASHI;UENO, HIROTAKA;TAKASE, HIROSHI
分类号 G06F13/42;H04L29/10;H04L12/40;H04L12/64;H04L12/70;H04L29/06;H04L29/08 主分类号 G06F13/42
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