<p>[PROBLEMS] To provide a multi-layer printed circuit board capable of assuring via hole connection reliability. [MEANS FOR SOLVING PROBLEMS] At the connection portion between the bottom of the filled via (60) and the cover plated layer (36a), the connection boundary plane is shifted downward from the upper surface of the cover plated layer (36a) by depth d1. Thus, the connection boundary plane where a crack is caused most easily is at a lower position than the upper surface position of the cover plated layer (36a) where the stress upon heat shrinkage becomes maximum. Accordingly, a crack is not caused easily and resistance against thermal stress can be enhanced.</p>
