发明名称 DATA SLICE CIRCUIT
摘要 PROBLEM TO BE SOLVED: To obtain a data slice circuit capable of correctly executing binarization when a maximum time of continuing the same signal level in a succeeding data section requiring correct binarization is longer than a section length of a preamble section for a fixed period of time without requiring the correct binarization, and also, capable of securing noise resistance. SOLUTION: When an output signal of a comparator 4 fluctuates for a fixed period of time, a converging voltage Vhpf of an HPF 3 is set to the same voltage as the reference voltage Vref0. When the output signal of the comparator 4 continues for a fixed period of time with a code 1, the converging voltage Vhpf of the HPF 3 is set to a voltage Vrefp1 higher than the reference voltage Vref0 by a prescribed fixed voltage. When the output signal of the comparator 4 continues for a fixed period of time with a code 0, a converging voltage Vhpf of an HPF 4 is set to a voltage Vrefn1 lower than the reference voltage Vref0 by a prescribed fixed voltage. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006261779(A) 申请公布日期 2006.09.28
申请号 JP20050073089 申请日期 2005.03.15
申请人 RENESAS TECHNOLOGY CORP 发明人 HARUHANA HIDEYO;YAMAMOTO SEIJI
分类号 H04L25/03 主分类号 H04L25/03
代理机构 代理人
主权项
地址
您可能感兴趣的专利