| 摘要 |
PROBLEM TO BE SOLVED: To obtain an integrated circuit layout designing method capable of LVS verification at an early stage of layout design. SOLUTION: A placement and routing means 101 performs wiring by allowing a short circuit and outputs a layout. A short circuit correcting means 102 removes a short-circuited part of the wiring and reconnects by changing to a newly defined temporary wiring layer. Further, a description of an interlayer connecting method between the temporary wiring layer and the original wiring layer is outputted to an interlayer connecting information file 111. A layout verification means 103 uses the corrected layout and an LVS rule file 112 reflecting the interlayer connecting method and performs LVS by a layout with the short-circuited part corrected to a correct connection by the temporary wiring layer. COPYRIGHT: (C)2006,JPO&NCIPI
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