发明名称 DEMULTIPLEXER CIRCUIT AND RECEIVING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To maximally utilize TS packet data included in TS data. SOLUTION: This demultiplexer circuit is composed as follows. The TS (Transport Stream) data T1 outputted from a demodulation part 20 are inputted to first/second synchronous processing parts 310, 320. A synchronization establishment signal C1 outputted from a synchronization generation circuit 250 is inputted to the second synchronous processing circuit 320. The second synchronous processing circuit 320 outputs the extracted TS data S3 and an error signal S5 on the basis of the synchronization establishment signal C1. A switching circuit 350 outputs the extracted TS data S3 designated by a data switching circuit 330 to an H264 decoder 40 when the error signal S5 designated by an error switching circuit 332 is in a high level. When the error signal S5 is in a low level, the switching circuit 350 outputs mute data to the H264 decoder 40. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006261775(A) 申请公布日期 2006.09.28
申请号 JP20050073054 申请日期 2005.03.15
申请人 CASIO COMPUT CO LTD 发明人 OKADA KUNIO
分类号 H04J11/00;H04N7/173;H04N21/4385;H04N21/4425 主分类号 H04J11/00
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