CLOCK DATA RECOVERY CIRCUITRY COUPLED WITH PROGRAMMABLE LOGIC DEVICE CIRCUITRY

摘要

PROBLEM TO BE SOLVED: To provide a clock data recovery circuitry which is provided on a programmable logic device or is coupled with the programmable logic device.

SOLUTION: A programmable logic device ("PLD") is installed with a programmable clock data recover ("CDR") circuitry to allow the PLD, to communicate via any of a large number of CDR signaling protocols. The CDR circuit may be integrated with the PLD, or it may be made wholly or partly on a separate integrated circuit. The circuit may be capable of CDR input, CDR output, or both. The CDR capability may be provided, in combination with other non-CDR signaling capability, such as non-CDR low voltage differential signaling ("LVDS"). The circuit may be a part of a large-scaled system.

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