Memory access control circuit

摘要

A data transfer request of a data processing device with respect to a synchronous memory is divided by a burst transfer length unit request dividing section into a plurality of data transfer requests in which a data transfer amount is an amount of data to be burst-transferred at a time and the data to be burst-transferred at a time is within a single memory bank. An assembling section assembles the divided data transfer requests into a plurality of new data transfer requests obtained by combining the divided data transfer requests, one for each memory bank.