发明名称 Information processing apparatus with configurable processor
摘要 In a processor, an operating unit executes an instruction within an instruction set, and a second operating unit executes other custom instructions. The second operating unit consists of a plurality of AND circuits, OR circuits, adders, selectors, and multiplexers. The information about which circuit should be combined with which circuit when the instruction is input is held in advance as structure information in a configuration memory. One piece of structure information corresponds to one custom instruction. The second operating unit in an optimum circuit structure determined based on this structure information executes the instruction. With this arrangement, it is possible to increase the processing speed than when the operating unit executes the processing.
申请公布号 US7114061(B2) 申请公布日期 2006.09.26
申请号 US20030627709 申请日期 2003.07.28
申请人 FUJITSU LIMITED 发明人 HIROSE YOSHIO;SAITO MIYOSHI;COUZIJN WOUTER
分类号 G06F7/00;G06F9/30;G06F9/22;G06F9/318;G06F9/38;G06F11/00;G06F17/50;H03K17/00 主分类号 G06F7/00
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