| 摘要 |
PROBLEM TO BE SOLVED: To provide a MIS transistor capable of simultaneously achieving a reduction of an S/D diffusion layer resistance and a reduction of a gate parasitic capacitance, and to provide a manufacturing method thereof. SOLUTION: As shown in Fig. 1, a MIS transistor has a semiconductor substrate 1, a source drain regions 2 formed on the substrate, and a gate electrode 6 provided in an upper part of a channel region between the source drain regions. In the MIS transistor, the upper surface of the source drain region provided so as to sandwich a channel forming surface is elevated from a channel forming surface 7, and is located on the side of the gate electrode; and the upper surface of the source drain region 2 has a substantially flat surface of a level elevated and located on the side of the gate electrode, and an inclined surface inclined from the level of this flat surface to the level of the channel forming surface. The shape of the gate electrode 6 surrounded by a gate insulating film provided on the upside of the channel forming surface is a shape of a sectional T-shape formed to be tapered through a step. COPYRIGHT: (C)2006,JPO&NCIPI
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