摘要 |
<p>An access discriminating circuit (4) discriminates between a first access operation, in which a column address (CADD), which is a burst address, is detected, a word line is updated, a new memory cell (MC) is selected and then stored data is read, and a second access operation, in which memory cells (MC) connected commonly to an already selected word line are selected by sequentially switching column selection switches, to output an discrimination signal (S). Operation condition information (Dx (DAx or/and DBx)), which is used for establishing a load condition in a dummy load circuit (5) or/and for establishing a pulse width of an equalization signal (EQ) in an amplifying control circuit (6), is stored in first and second storing parts (1,2) for each of the first and second access operations, and selected by a selector circuit (3) in accordance with the discrimination signal (S) for application to the dummy load circuit (5) or/and the amplifying control circuit (6). Operational conditions suitable for the respective access operations are selected.</p> |
申请人 |
SPANSION LLC;SPANSION JAPAN LIMITED;SHIMBAYASHI, KOJI;FURUYAMA, TAKAAKI;SHIBATA, KENJI |
发明人 |
SHIMBAYASHI, KOJI;FURUYAMA, TAKAAKI;SHIBATA, KENJI |