| 摘要 |
Methods and systems for locking a phase locked loop (PLL) are disclosed herein. A first impulse signal may be generated utilizing an input reference signal. A second impulse signal may be generated utilizing an input divided signal. A programmable delay signal may be generated based on the generated first impulse signal and the generated second impulse signal. The generation of the first impulse signal and the generation of the second impulse signal may be controlled via the generated programmable delay signal. The generated first impulse signal and the generated second impulse signal may be delayed utilizing a programmable delay. The delayed first impulse signal and the delayed second impulse signal may be ANDed to generate the programmable delay signal, and the generated programmable delay signal may comprise a reset signal.
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