发明名称 Comparison of two hierarchical netlist to generate change orders for updating an integrated circuit layout
摘要 A method and system for optimizing a netlist change order flow is disclosed, wherein a design layout created by a layout tool using a reference netlist is to be changed by a modified version of the netlist, and wherein both netlists are hierarchical comprising. Aspects of the present invention include comparing the modified netlist with the original netlist outside of the layout tool, and automatically generating at least one change order based on differences found between the two netlists. After the change order is generated, the change order is then applied to the design layout to generate a modified design layout.
申请公布号 US7111269(B2) 申请公布日期 2006.09.19
申请号 US20030693075 申请日期 2003.10.23
申请人 LSI LOGIC CORPORATION 发明人 SATAPATHY LALITA;RAMAN SANTHANAKRIS;BLINNE RICHARD
分类号 G06F9/455;G06F17/50 主分类号 G06F9/455
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