Gate bias circuit for MOS Charge Coupled Devices

摘要

A biasing circuit for use with a Charged Coupled Device (CCD) that creates a gate bias voltage by maintaining a model or surrogate representation of the surface potentials within the CCD storage and barrier regions. In one embodiment the invention is a bias circuit that includes at least a first and second model transistor for modeling the two regions. The first model transistor is connected to a supply voltage to provide a first reference voltage at a first node, and models the first charge storage region. A resistive circuit element is coupled between the first node N 1 and a second node N 2 in order to allow a step voltage to be developed. The second model transistor is in turn connected to the second node N 2 and provides the bias voltage at an output portion that can be used to control the gate of the barrier region. The model circuit therefore allows a proper bias voltage to be maintained through process and operating condition variations.