发明名称 System for measuring signal path resistance for an integrated circuit tester interconnect structure
摘要 Resistances of signal paths within a interconnect structure for linking input/output (I/O) ports of an integrated circuit (IC) tester to test points of an IC are measured by the IC tester itself. To do so the interconnect structure is used to link the tester's I/O ports to a similar arrangement of test points linked to one another through conductors. Drivers within the tester, which normally transmit digital test signals to IC test points via the I/O ports when the IC is under test, are modified so that they may also either transmit a constant current through the I/O ports or link the I/O ports to ground or other reference potential. The tester then transmits known currents though the signal paths interconnecting the tester's I/O ports. Existing comparators within the tester normally used to monitor the state of an IC's digital output signals are employed to measure voltage drops between the I/O ports, thereby to provide data from which resistance of signal paths within the interconnect structure may be computed.
申请公布号 US7109736(B2) 申请公布日期 2006.09.19
申请号 US20030750611 申请日期 2003.12.29
申请人 发明人
分类号 G01R31/26;G01R27/14;G01R31/319;G01R35/00 主分类号 G01R31/26
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