| 摘要 |
A dual-port modulator comprising a first Phase Locked Loop ('PLL') ( 15 ) including a first Voltage Controlled Oscillator ('VCO') ( 10 ), a first variable frequency divider ( 20 ), a first multi-accumulator sequence generator ( 21 ) responsive to a phase modulation signal for controlling the division ratio (1/Nr) of the first variable frequency divider, a first phase detector ( 30 ) responsive to the relative phases of the reference signal and the first frequency divider signal for producing a first control signal through a first low pass filter ( 40 ). The frequency synthesiser also comprises a second PLL ( 14 ) including a second VCO ( 201 ), the first control signal being applied to the tuning port of the second VCO ( 201 ), a second variable frequency divider ( 203 ), a second multi-accumulator sequence generator ( 204 ) responsive to a phase modulation signal ( 261 ) for controlling the division ratio (1/Nt) of the second variable frequency divider, and a second phase detector ( 202 ) responsive to the relative phases of the second VCO signal and the second frequency divider signal for applying a second control signal to the tuning port of the second VCO ( 201 ) through a second low pass filter ( 208 ), the first and second frequency dividers ( 20, 203 ) being arranged to divide the frequency of the first VCO signal, and the bandwidth of the first PLL ( 15 ) being substantially smaller than the bandwidth of the second PLL ( 14 ). The modulator is applicable in a transceiver also including a demodulator PLL ( 306, 307 ) including the second VCO ( 201 ), the modulator being arranged to be inactive during periods when the demodulator is active and the demodulator being arranged to be inactive during periods when the modulator is active, such as dual-standard transceiver operating according to WCDMA and PCS/DCS standards.
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