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发明名称
DEZENTRALE FEHLERTOLERANTE TAKTGENERIERUNG IN VLSI CHIPS
摘要
申请公布号
AT501510(A1)
申请公布日期
2006.09.15
申请号
AT20040001223
申请日期
2004.07.19
申请人
TECHNISCHE UNIVERSITAET WIEN
发明人
分类号
(IPC1-7):G06F1/14
主分类号
(IPC1-7):G06F1/14
代理机构
代理人
主权项
地址
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