发明名称 |
Pulse duty deterioration detection circuit |
摘要 |
A pulse duty deterioration detection circuit with a high monitoring precision is easily provided. The pulse duty deterioration detection circuit comprises a delay circuit comprised of a general-purpose gate circuit which generates a delayed synchronous to-be-monitored clock by delaying the to-be-monitored clock by a predetermined time, a latch circuit which detects based on the to-be-monitored clock and the delayed synchronous to-be-monitored clock that a value of a decrease in a pulse width to be determined by a pulse duty of the to-be-monitored clock becomes smaller than the predetermined time, and a flip-flop circuit which samples an output signal of the latch circuit based on the to-be-monitored clock.
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申请公布号 |
US7106116(B2) |
申请公布日期 |
2006.09.12 |
申请号 |
US20030689028 |
申请日期 |
2003.10.21 |
申请人 |
OKI ELECTRIC INDUSTRY CO., LTD. |
发明人 |
YAMADA TOSHIMI |
分类号 |
H03K5/06;H03K3/00;H03K5/156;H03K5/19;H03K5/26 |
主分类号 |
H03K5/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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